ADCs are used in a wide variety of fields as components within modules performing a large variety of tasks. In wireless communication systems, ADCs are widely used to, for example, convert a received analog signal into its digital form. See, e.g., IEEE Standard for information technology—telecommunications and information exchange between systems—Local and metropolitan area networks—Specific Requirements—part 11: wireless LAN medium access control (MAC) and physical layer (PHY) specifications—amendment 4: enhancements for very high throughput for operation in bands below 6 GHz, IEEE Std 802.11ac-2013 (Amendment to IEEE Std 802.11-2012), December 2013, which is hereby incorporated by reference in its entirety. Because of the speed of technological advance, there is always pressure to develop faster, smaller, and more efficient ADCs.
FIG. 1A has three simplified diagrams illustrating three types of ADCs: Flash, pipelined, and successive approximation register (SAR). See, e.g., Chen et al., “A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-m CMOS,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2669-2680 (December 2006), from which FIG. 1 is based and which is hereby incorporated by reference in its entirety.
FIG. 1A also shows their relative power requirements and speed capabilities. Because its conversion operations occur in parallel, Flash is fast, capable of generating the digital value in a single clock cycle, regardless of the number N of bits. However, having all of those operations running in parallel is an enormous power drain and having all of the Flash comparators/components requires a large area. In essence, Flash's resource usage and cost increases exponentially as the number of bits increases. Instead of a fully parallel construction like Flash, a pipelined ADC divides the process into several comparison stages, the number of which is proportional to the number of bits. However, the pipelined topology also has problems of increasing complexity and power consumption.
SAR performs the conversion from analog to digital over multiple clock cycles using essentially an analog comparator, a digital-to-analog converter (DAC), and an approximation register (as part of the decoder in FIG. 1A) which determines the digital bit values over successive clock cycles. An N-bit SAR ADC uses only one comparator and takes only N clock cycles to complete conversion. In other words, if the digital value comprises 10 bits (or, equivalently, if the analog voltage is being converted to one of 1024 possible digital values), the conversion takes ten clock cycles. The total power consumption is substantially less than the other ADC topologies and, even though its speed is a fraction of the Flash ADC, its overall power efficiency is still the best of the three. Moreover, unlike other ADC topologies, there is no standby current, further reducing power consumption.
SAR ADC technology scales well and, because certain analog components such as amplifiers are not required, SAR ADCs are suitable for deep submicron semiconductor manufacturing.
Most SAR ADCs have a charge redistribution architecture, which is described below in reference to FIGS. 1B and 1C.
FIG. 1B is a simplified diagram of an N-bit binary-weighted capacitive DAC which can be used in a SAR ADC, such as the one shown in FIG. 1A. It comprises an array of capacitances with varying binary weights. The first capacitor, having capacitance Ccommon, corresponds to the MSB of the N-bit digital value. The second-to-last capacitor, having capacitance C/2N-1, corresponds to the LSB of the N-bit digital value, while the last capacitor (having the same capacitance) is the termination capacitance for the DAC. Each capacitor (except the last) corresponds to a bit value in the N-bit digital value from highest to lowest. Generally speaking, each capacitor, starting with the MSB, is tested per clock cycle to determine whether it is a 1 or a 0. In simplistic terms, the resulting voltage should be the quantized version of the input voltage, where each capacitor switch will indicate a 1 or 0. As would be understood by one of ordinary skill in the art, the actual process is much more complex, involves many more steps and components, and, perhaps most importantly, the specific architecture used may differ widely from the one shown in FIG. 1B. The present description focuses on the pertinent matters of interest.
FIG. 1C is a diagram of an example of a binary-weighted capacitor DAC for conversion to a 5-bit value. FIG. 1C shows the DAC at the last step of the process, where the bits have been determined, and is based on a drawing from the seminal paper on charge redistribution ADCs, McCreary et al., “All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques,” IEEE J. Solid-State Circuits, vol. SC-10, no. 6, pp. 371-379 (December 1975), which is hereby incorporated by reference in its entirety.
In FIG. 1C, the bit values can be seen above each capacitor and correspond to the setting of the switches beneath. Because b4=0, b3=1, b2=0, b1=0, and b0=1, the binary digital value of VIN is 01001, which is the decimal value 9. FIG. 1C also makes it more clear how the capacitances are binary weighted: the capacitance corresponding to b4 (=24=16) is C; the capacitance corresponding to b3 (=23=8) is C/2; the capacitance corresponding to b2 (=22=4) is C/4; the capacitance corresponding to b1 (=21=2) is C/8; and the capacitance corresponding to b0 (=20=1) is C/16—i.e., the unit value is one-sixteenth the highest value.
As stated above, N decisions/clock cycles are required for an N-bit SAR ADC, and each decision must be accurate to the full resolution of the converter. The sequential nature of the algorithm makes it difficult to achieve both high speed and high accuracy. One of the challenges for charge redistribution architecture is the phenomena known as settling, which refers to the time it takes for the unstable ringing of a DAC capacitor to settle down after being switched to a new value. This occurs, to greater or lesser effect, at each clock cycle/decision, and can cause performance degradation. A simple way to remove the effects of ringing is to allow greater time between decisions, making the process even longer.
Another approach to ringing, as well as other problems with SAR ADC accuracy, is the use of redundancy, by, for example, using non-binary weighting (i.e., based on lower values than 2) (see, e.g., F. Kuttner, “A 1.2V 10b 20 MSamples/s Non-binary successive Approximation ADC in 0.13 um CMOS,” 2002 IEEE Int'l Solid-State Circuits Conf. (ISSCC 2002), Session 10—High-speed ADCs, section 10.6, which is hereby incorporated by reference in its entirety) and/or by adding more capacitors (see, e.g., C.-C. Liu et al., “A 10b 100 MS/s 1.13 mW SAR ADC with Binary-Scaled Error Compensation,” 2010 IEEE Intl Solid-State Circuits Conf. (ISSCC 2010) Dig. Tech. Papers, pp. 386-387, which is hereby incorporated by reference in its entirety). However, redundancy inevitably leads to additional components, logic, wiring, bit decisions/clock cycles, and so on.